1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a method for manufacturing the semiconductor device.
2. Description of the Related Art
In the rapidly evolving integrated circuit industry, developmental trend is toward high performance, miniaturization, and high operating speeds. Additionally dynamic random access memory (DRAM) fabrication methods have developed rapidly. In particular, increase of large memory capacity is an important objective for DRAM designers.
Typically, current DRAM cells include a transistor and a capacitor. Since the capacity of current DRAM has reached 512 MB and above to 1 GB, the size of the memory cells and transistors has narrowed to meet demands for higher integration, higher memory capacity and higher operating speeds. In conventional planar transistor fabrication, however, more useable surface area on an integrated circuit (chip) is required, making it difficult to meet the previously mentioned demands. Accordingly, vertical transistor technology has been applied to DRAM fabrication with the goal of reducing the area occupied by the transistor and the capacitor on the semiconductor substrate. The conventional planar transistor fabrication requires a large surface area on the chip, and cannot accomplish the demand for high integration. Conversely, vertical transistor technology can improve upon the disadvantages of the conventional semiconductor memory cell, and is positioned to become a mainstream semiconductor memory cell fabrication method.
Generally, various thicknesses of gate dielectric layers must be fabricated in memory devices so that various threshold voltages can be provided. However, the requirement makes the fabricating process more complex. Therefore, it is necessary to create a new fabricating method or process for solving the above-described issues.